1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of fabricating a semiconductor device such as a transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also requires reducing the size and area of electrical contacts to active areas, such as N.sup.+ (P.sup.+) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor. As the size and area of the electrical contacts to the active areas get smaller, the active area contact resistance increases. Increased active area contact resistance is undesirable for a number of reasons. For example, increased active area contact resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor.
Typically, depositing titanium (Ti) or cobalt (Co) on the active area electrical contacts may decrease active area contact resistance. The Ti may then be silicided by annealing with a heat-treatment to form titanium silicide (TiSi.sub.2) at the active area electrical contacts (self-aligned silicidation or salicidation). The salicided TiSi.sub.2 lowers active area contact resistance.
As shown in FIG. 1, a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor) 100 may be formed on a semiconducting substrate 105, such as doped-silicon. The MOS transistor 100 may have a doped-poly gate 110 formed above a gate oxide 115 formed above the semiconducting substrate 105. The doped-poly gate 110 and the gate oxide 115 may be separated from N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 of the MOS transistor 100 by dielectric spacers 125. The dielectric spacers 125 may be formed above N.sup.- -doped (P.sup.- -doped) lightly doped drain (LDD) regions 130.
The N.sup.- -doped (P.sup.- -doped) LDD regions 130 are typically provided to reduce the magnitude of the maximum channel electric field found close to the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 of the MOS transistor 100, and, thereby, to reduce the associated hot-carrier effects. The lower (or lighter) doping of the N.sup.- -doped (P.sup.- -doped) LDD regions 130, relative to the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 of the MOS transistor 100, reduces the magnitude of the maximum channel electric field found close to the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 of the MOS transistor 100, but increases the source-to-drain resistances of the N.sup.- -doped (P.sup.- -doped) LDD regions 130.
As shown in FIG. 2, a Ti metal layer 235 may be blanket-deposited on the MOS transistor 100 shown in FIG. 1 and then subjected to an initial rapid thermal anneal (RTA) process performed at a temperature ranging from approximately 450-800.degree. C. for a time ranging from approximately 15-60 seconds. At surfaces 240 of active areas 245, such as the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 and the doped-poly gate 110, exposed Si reacts upon heating with the Ti metal layer 235 to form TiSi.sub.2 at the surfaces 240 of the active areas 245. The Ti metal layer 235 is not believed to react with the dielectric spacers 125 upon heating.
As shown in FIG. 3, a wet chemical strip of the Ti metal layer 235 removes excess, unreacted portions (not shown) of the Ti metal layer 235, leaving behind the salicided TiSi.sub.2 350 only at and below the surfaces 240 of the active areas 245. The salicided TiSi.sub.2 350 may then be subjected to a final RTA process performed at a temperature ranging from approximately 800-1000.degree. C. for a time ranging from approximately 10-60 seconds.
However, even though conventional salicided TiSi.sub.2 (or salicided CoSi.sub.2) lowers the contact resistances of the active areas 245, such as the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120 and the doped-poly gate 110, the N.sup.- -doped (P.sup.- -doped) LDD regions 130 continue to degrade the device drive current, and the source/drain current through the device, because of the higher resistances of the N.sup.- -doped (P.sup.- -doped) LDD regions 130. The overall source-to-drain resistance, even with the conventional salicided TiSi.sub.2 350 in the N.sup.+ -doped (P.sup.+ -doped) source/drain regions 120, is significantly determined by the lower dopings, and, hence, higher resistances, of the N.sup.- -doped (P.sup.- -doped) LDD regions 130.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.